Abstract

This paper describes the HW/SW Codesign FPGA-based architecture of a log-normally distributed B-ACOSD CFAR target detector for radar systems in the abstract. The complete CFAR system is evaluated to see which components need to be strengthened so that the detection procedure can be carried out in real time. To ensure the CFAR Architecture is fully optimised, we have devoted careful attention to the Altera environment's custom instruction strategy. The CFAR detector is a hybrid hardware/software setup. The Avalon switch fabric allows the hardware modules to talk to the NIOS II processor, which runs the software. The on-chip memory and custom logic components complement the universal asynchronous receiver/transmitter (UART) and JTAG (JTAG) interfaces. The suggested SoC is verified and tested with the help of an Altera Stratix IV EP4SGX230KF4C2 running at 250MHz. 
We improved the efficiency of our embedded target detection system by fusing hardware and software approaches. When compared to a software-only solution, this resulted in a 0.45µs reduction in overall latency.